1. Technical Field
Various embodiments generally relate to a data output circuit, and more particularly to a data output circuit for generating a data output clock to improve a data window width.
2. Related Art
Double data rate (DDR) synchronous memory apparatuses are configured to transfer data on both the rising and falling edges of a clock signal.
For example, when a synchronous DRAM (SDRAM) communicates with a memory controller, the SDRAM transmit and receive data through data pins (e.g., DQ). When data is read from the SDRAM through the data pins, the memory controller reads data using a data strobe signal (e.g., DQS). When the memory controller writes to the SDRAM, data pins have the data to be written according to the data strobe signal.
A DDR SDRAM outputs data to an external device such as the memory controller in synchronization with the rising edge or falling edge of the data strobe signal. Also, data are written to the DDR SDRAM in synchronization with the data strobe signal.
Therefore, the slew rate and the duty cycle of the data strobe signal are supposed to be controlled to meet a requirement of DDR SDRAM standards.
However, when a skew difference occurs in rising clocks and falling clocks, which are required for generation of a data strobe signal, due to PVT variation or a difference in the characteristics of the PMOS and NMOS of a transistor, the duty ratio of the data strobe signal may be distorted.
It is very important to accurately control the duty ratio of a clock in a semiconductor memory device. When the duty ratio of a clock is not controlled, a narrow pulse width of an output signal reduces a timing margin. In a high-speed operation, this may cause incorrect data to be received.